1. Field of the Invention
This invention relates to a light emitting device, more particularly to a high efficient light emitting device including a substrate that has a plurality of closed pores formed therein.
2. Description of the Related Art
Since light emitting diodes have a relatively small size, they have been widely utilized in back light modules, computers, traffic lights, and outdoor displays. However, the application of the light emitting diode encounters a problem of insufficient light output. Skilled artisans have tried to solve the problem in various aspects. For example, epitaxial technology has been developed to increase concentrations of donors and acceptors in an active layer of the light emitting diode, and to decrease dislocation density of the active layer. Nevertheless, it is difficult to increase the concentration of acceptors in the active layer, particularly in a gallium nitride (GaN) semiconductor system having a wide energy gap. Since there is a relatively high degree of lattice mismatch between sapphire substrate and gallium nitride layer formed on the sapphire substrate in the conventional light emitting diode, it is difficult to make a breakthrough in reducing dislocation density of the active layer.
Referring to FIG. 1, a conventional semiconductor light emitting device, which is described in Taiwanese Patent Publication No. 561632, includes a sapphire substrate 10, an n-type semiconductor layer 11 formed on the sapphire substrate 10, a light emitting layer 12 that is formed on the n-type semiconductor layer 11 and that serves as a light emitting layer to emit light beams within a predetermined wavelength range, and a p-type semiconductor layer 13 formed on the light emitting layer 12.
The sapphire substrate 10 is formed with a plurality of trenches 14, and a plurality of protrusions 102 separated by the trenches 14. The sapphire substrate 10 has a main face defined as C face (0001). Each of the trenches 14 is defined by a trench-defining bottom surface 101 and a trench-defining peripheral surface 103. The trench-defining peripheral surface 103 is generally parallel to a stabilized growth surface (i.e. M surface {1 100}) of the n-type semiconductor layer 11, so as to form the n-type semiconductor layer 11 on the sapphire substrate 10 without crystal defects. Each of the trenches 14 has a depth of 1 μm and a size of 10 μm, and is spaced apart from an adjacent one of the trenches 14 by a center-to-center distance of 10 μm.
FIG. 2 illustrates how the n-type semiconductor layer 11 is grown on the protrusions 102 of the sapphire substrate 10, and the trench-defining bottom surface 101 and the trench-defining peripheral surface 103 of each trench 14. For simplicity, only one protrusion 102 is shown. When the n-type semiconductor layer 11 starts growing from the sapphire substrate 10, the growth rate of the n-type semiconductor layer 11 on the trench-defining bottom surface 101 and the protrusion 102 is relatively higher than that on the trench-defining peripheral surface 103. As shown in FIG. 3, when the n-type semiconductor layer 11 continues to grow to an extent such that the n-type semiconductor layer 11 on the trench-defining bottom surface 101 intersects the n-type semiconductor layer. 11 on the protrusion 102, the growth rate of the n-type semiconductor layer 11 at the intersection area becomes faster than that at the remaining area. The resultant n-type semiconductor layer 11 thus formed on the sapphire substrate 10 is planar and void-free, and has a relatively good crystallinity.
By virtue of the trenches 14 in the sapphire substrate 10, the light beams from the light emitting layer 12 can scatter and diffract in the light emitting device so as to reduce absorption and decay of the light beams due to lateral transmission and so as to enhance external quantum efficiency of the light emitting device. In addition, since no crystal defect is produced in the interface between the sapphire substrate 10 and the n-type semiconductor layer 11, the internal quantum efficiency of the light emitting device is also enhanced.
Nevertheless, as well-known to those skilled in the crystallography field, lattice mismatch frequently occurs at the interface between two materials that have different lattice constants. Dislocation density (i.e. line defects) resulting from the lattice mismatch will be higher with a larger contact area between the two materials.